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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 6 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
99
Voted
ISCAS
2005
IEEE
167views Hardware» more  ISCAS 2005»
15 years 6 months ago
Low-power log-MAP turbo decoding based on reduced metric memory access
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...
Dong-Soo Lee, In-Cheol Park
115
Voted
ISESE
2005
IEEE
15 years 6 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
ISESE
2005
IEEE
15 years 6 months ago
Effects of pair programming at the development team level: an experiment
We studied the effects of pair programming in a team context on productivity, defects, design quality, knowledge transfer and enjoyment of work. Randomly formed three pair program...
Jari Vanhanen, Casper Lassenius
ISM
2005
IEEE
88views Multimedia» more  ISM 2005»
15 years 6 months ago
Hybrid Bitrate/PSNR Control for H.264 Video Streaming to Roaming Users
In wireless communications, the available throughput depends on several parameters, like physical layer, base station distance, fading and interference. Users experience changes i...
Fabio De Vito, Federico Ridolfo, Juan Carlos De Ma...