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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
15 years 6 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
ISSRE
2005
IEEE
15 years 3 months ago
Providing Test Quality Feedback Using Static Source Code and Automatic Test Suite Metrics
A classic question in software development is “H ow much testing is enough?” Aside from dynamic coverage-based metrics, there are few measures that can be used to provide guid...
Nachiappan Nagappan, Laurie A. Williams, Jason Osb...
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 3 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
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ICCV
2005
IEEE
15 years 11 months ago
Learning Non-Negative Sparse Image Codes by Convex Programming
Example-based learning of codes that statistically encode general image classes is of vital importance for computational vision. Recently, non-negative matrix factorization (NMF) ...
Christoph Schnörr, Matthias Heiler
ICIP
2005
IEEE
15 years 3 months ago
Frame based multiple description image coding in the wavelet domain
Multiple description codes generated by quantized frame expansions have been shown to perform well on erasure channels when compared to traditional channel codes. In this paper we...
Sumohana S. Channappayya, Joonsoo Lee, Robert W. H...