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CODES
2006
IEEE
15 years 5 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
CODES
2006
IEEE
15 years 5 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
CODES
2006
IEEE
15 years 3 months ago
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel suppo...
Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Bro...
IPPS
2006
IEEE
15 years 5 months ago
Techniques and tools for dynamic optimization
Traditional code optimizers have produced significant performance improvements over the past forty years. While promising avenues of research still exist, traditional static and p...
Jason Hiser, Naveen Kumar, Min Zhao, Shukang Zhou,...
EMSOFT
2006
Springer
15 years 2 months ago
An analysis framework for network-code programs
Distributed real-time systems require a predictable and verifiable mechanism to control the communication medium. Current real-time communication protocols are typically independe...
Madhukar Anand, Sebastian Fischmeister, Insup Lee