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ARITH
1999
IEEE
15 years 8 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
GROUP
1999
ACM
15 years 8 months ago
Getting some perspective: using process descriptions to index document history
Process descriptions are used in workflow and related systems to describe the flow of work and organisational responsibility in business processes, and to aid in coordination. How...
Paul Dourish, Richard Bentley, Rachel Jones, Allan...
SPAA
1999
ACM
15 years 8 months ago
Recursive Array Layouts and Fast Parallel Matrix Multiplication
Matrix multiplication is an important kernel in linear algebra algorithms, and the performance of both serial and parallel implementations is highly dependent on the memory system...
Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K....
HPCA
1999
IEEE
15 years 8 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
HPCA
1999
IEEE
15 years 8 months ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González