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118
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DAC
1999
ACM
15 years 8 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
133
Voted
DAC
1999
ACM
15 years 8 months ago
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
Vijay Sundararajan, Keshab K. Parhi
143
Voted
DAC
1999
ACM
15 years 8 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
138
Voted
DAC
1999
ACM
15 years 8 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
DAC
1999
ACM
15 years 8 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung