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114
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TCAD
2002
15 years 8 days ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
TCAD
2002
15 years 8 days ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
76
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TCAD
2002
15 years 8 days ago
2002
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
102
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TCAD
2002
15 years 8 days ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
98
Voted
TCAD
2002
15 years 8 days ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...