Information Retrieval (IR) systems are built with different goals in mind. Some IR systems target high precision that is to have more relevant documents on the first page of their...
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
The results of a project aimed to the study, reconstruction and presentation to the public of a monument disassembled and dispersed, the mausoleum of the emperor Arrigo VII, are p...
Clara Baracchini, Antonio Brogi, Marco Callieri, L...
We define a language whose type system, incorporating session types, allows complex protocols to be specified by types and verified by static typechecking. A session type, asso...