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2006
IEEE
100views Hardware» more  DATE 2006»
16 years 6 days ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
16 years 6 days ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 6 days ago
Equivalence verification of arithmetic datapaths with multiple word-length operands
Abstract: This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have diļ¬...
Namrata Shekhar, Priyank Kalla, Florian Enescu
DATE
2006
IEEE
132views Hardware» more  DATE 2006»
16 years 6 days ago
Energy reduction by workload adaptation in a multi-process environment
Reducing energy consumption is an important issue in modern computers. Dynamic power management (DPM) has been extensively studied in recent years. One approach for DPM is to adju...
Changjiu Xian, Yung-Hsiang Lu
DATE
2006
IEEE
107views Hardware» more  DATE 2006»
16 years 6 days ago
Time domain model order reduction by wavelet collocation method
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian...
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