- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...
Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lind...
In this paper we propose an intrinsic developmental algorithm that is designed to allow a mobile robot to incrementally progress through levels of increasingly sophisticated behav...
Douglas S. Blank, Deepak Kumar, Lisa Meeden, James...
Abstract—Low-power, single-chip integrated systems are prevailing in remote applications due to the increasing power and delay cost of inter-chip communication compared to on-chi...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...