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2005
IEEE
187views Hardware» more  DATE 2005»
15 years 3 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
ICIP
2005
IEEE
15 years 11 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
AIED
2005
Springer
15 years 3 months ago
Explainable Artificial Intelligence for Training and Tutoring
This paper describes an Explainable Artificial Intelligence (XAI) tool that allows entities to answer questions about their activities within a tactical simulation. We show how XAI...
H. Chad Lane, Mark G. Core, Michael van Lent, Stev...
ICDE
2005
IEEE
137views Database» more  ICDE 2005»
15 years 11 months ago
Extending Relational Database Systems to Automatically Enforce Privacy Policies
Databases are at the core of successful businesses. Due to the voluminous stores of personal data being held by companies today, preserving privacy has become a crucial requiremen...
Rakesh Agrawal, Paul Bird, Tyrone Grandison, Jerry...
ETFA
2005
IEEE
15 years 3 months ago
RTnet - a flexible hard real-time networking framework
In this paper, the Open Source project RTnet is presented. RTnet provides a customisable and extensible framework for hard real-time communication over Ethernet and other transpor...
J. Kiszka, B. Wagner