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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 3 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
15 years 3 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
HICSS
2005
IEEE
117views Biometrics» more  HICSS 2005»
15 years 3 months ago
MobCon: A Generative Middleware Framework for Java Mobile Applications
While dedicated technologies such as e.g., Sun’s J2ME MIDP offer a simple programming model for mobile applications, appropriate support for modularizing the implementation of t...
Vasian Cepa, Mira Mezini
HICSS
2005
IEEE
153views Biometrics» more  HICSS 2005»
15 years 3 months ago
SOTIP as a Model for Outsourcing of Telecom Services for the Public Sector
The political intentions for the past 20 years have broadly speaking been to reduce the number of publicly owned and publicly run activities. Outsourcing is an often applied way t...
Helena Lindskog
ICAC
2005
IEEE
15 years 3 months ago
Self-Optimizing Architecture for QoS Provisioning in Differentiated Services
This paper presents a scalable and self-optimizing architecture for Quality-of-Service (QoS) provisioning in the Differentiated Services (DiffServ) framework. The proposed archite...
Daniel Yagan, Chen-Khong Tham