In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
While dedicated technologies such as e.g., Sun’s J2ME MIDP offer a simple programming model for mobile applications, appropriate support for modularizing the implementation of t...
The political intentions for the past 20 years have broadly speaking been to reduce the number of publicly owned and publicly run activities. Outsourcing is an often applied way t...
This paper presents a scalable and self-optimizing architecture for Quality-of-Service (QoS) provisioning in the Differentiated Services (DiffServ) framework. The proposed archite...