Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Modern high performance processors employ advanced techniques for thermal management, which rely on accurate readings of on-die thermal sensors. As the importance of thermal effec...
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...