Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited b...
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...