In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...