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DATE
1998
IEEE
88views Hardware» more  DATE 1998»
15 years 1 months ago
Functional Scan Chain Testing
Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (T...
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-...
DATE
1998
IEEE
82views Hardware» more  DATE 1998»
15 years 1 months ago
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
15 years 1 months ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
15 years 1 months ago
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions
Simple disjunctive decomposition is a special case of logic function decompositions, where variables are divided into two disjoint sets and there is only one newly introduced vari...
Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
CRYPTO
1998
Springer
83views Cryptology» more  CRYPTO 1998»
15 years 1 months ago
Time-Stamping with Binary Linking Schemes
We state the basic requirements for time-stamping systems applicable as the necessary support to the legal use of electronic documents. We analyze the main drawbacks of the time-st...
Ahto Buldas, Peeter Laud, Helger Lipmaa, Jan Wille...