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date 2000
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Date Warehouse Design
16 years 5 hour ago
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Stefano Rizzi, Matteo Golfarelli
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2000
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Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model
16 years 14 hour ago
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Youxin Gao, D. F. Wong
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2000
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CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
16 years 14 hour ago
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Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
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2000
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Cost and Benefit Models for Logic and Memory BIST
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Juin-Ming Lu, Cheng-Wen Wu
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2000
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Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion
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Juan M. Díez, Juan Carlos López
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