179 search results - page 9 / 36 » date 2002 |
DATE
2002
IEEE
15 years 5 months ago
2002
IEEE
This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A ...
DATE
2002
IEEE
15 years 5 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
95
Voted
DATE
2002
IEEE
15 years 5 months ago
2002
IEEE
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
96
Voted
DATE
2002
IEEE
15 years 5 months ago
2002
IEEE
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
89
Voted
DATE
2002
IEEE
15 years 5 months ago
2002
IEEE
After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packin...