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2003
IEEE
96views Hardware» more  DATE 2003»
15 years 3 months ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
15 years 3 months ago
Circuit and Platform Design Challenges in Technologies beyond 90nm
There are already a huge number of problems for silicon designers and it is likely to just get worse. Many of these problems are technical associated with shrinking geometries and...
Bill Grundmann, Rajesh Galivanche, Sandip Kundu
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
15 years 3 months ago
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
Michael Nicolaidis, Nadir Achouri, Slimane Boutobz...
DATE
2003
IEEE
81views Hardware» more  DATE 2003»
15 years 3 months ago
Figure of Merit Based Selection of A/D Converters
A new method for selecting analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit is introduced that includes both specific...
Martin Vogels, Georges G. E. Gielen
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 3 months ago
Interconnect Planning with Local Area Constrained Retiming
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and ...
Ruibing Lu, Cheng-Kok Koh