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94
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
112
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
109
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the CAD tools to manipulate the designs within the tools. These f...
79
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...