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2003
IEEE
97views Hardware» more  DATE 2003»
15 years 3 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
79
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DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 3 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
15 years 3 months ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
70
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DATE
2003
IEEE
118views Hardware» more  DATE 2003»
15 years 3 months ago
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints
The model-based methodology has proven to be effective for fast and low-cost development of embedded software. In the model-based development process, transforming a software stru...
Sharath Kodase, Shige Wang, Kang G. Shin
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
15 years 3 months ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...