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2003
IEEE
132views Hardware» more  DATE 2003»
15 years 3 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 3 months ago
Area Fill Generation With Inherent Data Volume Reduction
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
72
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DATE
2003
IEEE
90views Hardware» more  DATE 2003»
15 years 3 months ago
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys
MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A...
Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nad...
74
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DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 3 months ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...
93
Voted
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 3 months ago
Run-Time Management of Logic Resources on Reconfigurable Systems
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...