299 search results - page 39 / 60 » date 2003 |
67
Voted
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
74
Voted
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...
86
Voted
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...