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    Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
    15 years 7 months ago
    Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
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    Peter Feldmann
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    Synthesis of Reversible Logic
    15 years 7 months ago
    Synthesis of Reversible Logic
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    Abhinav Agrawal, Niraj K. Jha
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    Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
    15 years 7 months ago
    Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
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    Per Bjesse, James H. Kukula
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    2004
    IEEE
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    Model-Based Specification and Execution of Embedded Real-Time Systems
    15 years 7 months ago
    Model-Based Specification and Execution of Embedded Real-Time Systems
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    Tim Schattkowsky, Wolfgang Müller 0003
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    2004
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    Automatic Generation of Validation Stimuli for Application-Specific Processors
    15 years 7 months ago
    Automatic Generation of Validation Stimuli for Application-Specific Processors
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    O. Goloubeva, Matteo Sonza Reorda, Massimo Violant...
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