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2004
IEEE
129views Hardware» more  DATE 2004»
15 years 3 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...
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DATE
2004
IEEE
102views Hardware» more  DATE 2004»
15 years 3 months ago
High Security Smartcards
New consumer appliances such as PDA, Set Top Box, GSM/UMTS terminals enable an easy access to the internet and strongly contribute to the development of ecommerce and m-commerce s...
Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P...
DATE
2004
IEEE
109views Hardware» more  DATE 2004»
15 years 3 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 3 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
15 years 3 months ago
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currentl...
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha