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2004
IEEE
82views Hardware» more  DATE 2004»
15 years 1 months ago
Managing Don't Cares in Boolean Satisfiability
Advances in Boolean satisfiability solvers have popularized their use in many of today's CAD VLSI challenges. Existing satisfiability solvers operate on a circuit representat...
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
15 years 1 months ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 1 months ago
Arithmetic Reasoning in DPLL-Based SAT Solving
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 1 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 1 months ago
Formal Refinement and Model Checking of an Echo Cancellation Unit
This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML sta...
Alexander Krupp, Wolfgang Müller 0003, Ian Ol...