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2004
IEEE
138views Hardware» more  DATE 2004»
15 years 1 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 1 months ago
GRAAL - A Development Framework for Embedded Graphics Accelerators
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
DATE
2004
IEEE
128views Hardware» more  DATE 2004»
15 years 1 months ago
An Assembler Driven Verification Methodology (ADVM)
This paper presents an overview of an assembler driven verification methodology (ADVM) that was created and implemented for a chip card project at Infineon Technologies AG [2]. Th...
John S. MacBeth, Dietmar Heinz, Ken Gray
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 1 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
15 years 1 months ago
Extremely Low-Power Logic
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large l...
Christian Piguet, Jacques Gautier, Christoph Heer,...