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117
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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 5 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
80
Voted
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
15 years 5 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
100
Voted
DATE
2005
IEEE
144views Hardware» more  DATE 2005»
15 years 5 months ago
Context Sensitive Performance Analysis of Automotive Applications
Accurate timing analysis is key to efficient embedded system synthesis and integration. While industrial control software systems are developed using graphical models, such as Ma...
Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabia...
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
15 years 5 months ago
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
This paper presents a new mathematical approach to modeling EM wave coupling noise so that it can be easily integrated into chip-level noise analysis tools. The new method employs...
Baohua Wang, Pinaki Mazumder
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 2 months ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan