A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects. The propose...
Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen W...
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...
A considerable amount of research in case-based reasoning (CBR) has recently focused on conversational CBR as a means of providing more effective support for interactive problem ...