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2005
IEEE
132views Hardware» more  DATE 2005»
15 years 3 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
66
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DATE
2005
IEEE
120views Hardware» more  DATE 2005»
15 years 3 months ago
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting...
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
75
Voted
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 3 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
15 years 3 months ago
C Compiler Retargeting Based on Instruction Semantics Models
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, ...
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
15 years 3 months ago
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
The widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security. Most of those embedded systems (pay-TV,...
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, P...