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DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid’s...
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DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...