Sciweavers

387 search results - page 47 / 78
» date 2005
Sort
View
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 3 months ago
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
90
Voted
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
15 years 3 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 4 days ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
79
Voted
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
15 years 4 days ago
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
Charlotte Soens, Geert Van der Plas, Piet Wambacq,...
134
Voted
CP
2005
Springer
15 years 3 months ago
Planning and Scheduling to Minimize Tardiness
We combine mixed integer linear programming (MILP) and constraint programming (CP) to minimize tardiness in planning and scheduling. Tasks are allocated to facilities using MILP an...
John N. Hooker