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2006
IEEE
88views Hardware» more  DATE 2006»
15 years 4 months ago
Using conjugate symmetries to enhance gate-level simulations
State machine based simulation of Boolean functions is substantially faster if the function being simulated is symmetric. Unfortunately function symmetries are comparatively rare....
Peter M. Maurer
DATE
2006
IEEE
117views Hardware» more  DATE 2006»
15 years 4 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 4 months ago
Cell delay analysis based on rate-of-current change
Abstract - A cell delay model based on rate-of-currentchange is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More pre...
Shahin Nazarian, Massoud Pedram
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
15 years 4 months ago
A practical method to estimate interconnect responses to variabilities
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the ...
Frank Liu
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 4 months ago
Software implementation of Tate pairing over GF(2m)
Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of su...
Guido Bertoni, Luca Breveglieri, Pasqualina Fragne...