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DATE
2006
IEEE
94views Hardware» more  DATE 2006»
15 years 4 months ago
Reuse-based test access and integrated test scheduling for network-on-chip
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
15 years 4 months ago
Test set enrichment using a probabilistic fault model and the theory of output deviations
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
15 years 4 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
15 years 4 months ago
Statistical timing analysis with path reconvergence and spatial correlations
State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated. Spatial correlation and correlation caused by p...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
15 years 4 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...