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2006
IEEE
86views Hardware» more  DATE 2006»
15 years 4 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....
79
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DATE
2006
IEEE
125views Hardware» more  DATE 2006»
15 years 4 months ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
15 years 4 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
66
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DATE
2006
IEEE
102views Hardware» more  DATE 2006»
15 years 4 months ago
Pseudorandom functional BIST for linear and nonlinear MEMS
Pseudorandom test techniques are widely used for measuring the impulse response (IR) for linear devices and Volterra kernels for nonlinear devices, especially in the acoustics dom...
Achraf Dhayni, Salvador Mir, Libor Rufer, Ahc&egra...
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
15 years 4 months ago
Minimizing test power in SRAM through reduction of pre-charge activity
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hash...