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108
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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 4 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
15 years 4 months ago
Test generation for combinational quantum cellular automata (QCA) circuits
— In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent at...
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
67
Voted
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
15 years 4 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
91
Voted
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
15 years 4 months ago
Microarchitectural floorplanning under performance and thermal tradeoff
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...
Michael B. Healy, Mario Vittes, Mongkol Ekpanyapon...
80
Voted
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
15 years 4 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...