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2006
IEEE
94views Hardware» more  DATE 2006»
15 years 4 months ago
Procrastinating voltage scheduling with discrete frequency sets
This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload in...
Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, ...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 4 months ago
Is "Network" the next "Big Idea" in design?
As the complexity of nowadays systems continues to grow, we are moving away from creating individual components from scratch, toward methodologies that emphasize composition of re...
Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiov...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 4 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
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DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 4 months ago
An improved RF loopback for test time reduction
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Su...
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 4 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...