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2006
IEEE
104views Hardware» more  DATE 2006»
15 years 4 months ago
Optimizing sequential cycles through Shannon decomposition and retiming
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
Cristian Soviani, Olivier Tardieu, Stephen A. Edwa...
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
15 years 4 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 4 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
15 years 4 months ago
On the verification of automotive protocols
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pa...
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
15 years 4 months ago
Double-sampling single-loop sigma-delta modulator topologies for broadband applications
This paper presents novel double sampling high order single-loop sigma-delta modulator structures for wideband applications. To alleviate the quantization noise folding into the i...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...