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2006
IEEE
151views Hardware» more  DATE 2006»
15 years 4 months ago
40Gbps de-layered silicon protocol engine for TCP record
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
H. Shrikumar
90
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IEEEMM
2010
102views more  IEEEMM 2010»
14 years 8 months ago
Printing in a Digital Age
:  Printing in a Digital Age Qian Lin, Jerry Liu, Daniel Tretter HP Laboratories HPL-2010-113 Paper has been used as an information medium for almost two thousand years. But dur...
Qian Lin, Jerry Liu, Daniel Tretter
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
15 years 4 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
15 years 4 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 4 months ago
Performance analysis of greedy shapers in real-time systems
— Traffic shaping is a well-known technique in the area of networking and is proven to reduce global buffer requirements and end-to-end delays in networked systems. Due to these...
Ernesto Wandeler, Alexander Maxiaguine, Lothar Thi...