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DATE
2007
IEEE
112views Hardware» more  DATE 2007»
15 years 4 months ago
Compact hardware design of Whirlpool hashing core
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
Timo Alho, Panu Hämäläinen, Marko H...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
15 years 4 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
61
Voted
DATE
2007
IEEE
116views Hardware» more  DATE 2007»
15 years 4 months ago
Testable design for advanced serial-link transceivers
This paper describes a DfT solution for modern seriallink transceivers. We first summarize the architectures of the Crosstalk Canceller and the Equalizer used in advanced transcei...
Mitchell Lin, Kwang-Ting (Tim) Cheng
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 4 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 4 months ago
Impact of process variations on multicore performance symmetry
Multi-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed—and that software expects—to be s...
Eric Humenay, David Tarjan, Kevin Skadron