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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 4 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
15 years 4 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
15 years 4 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 4 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
DATE
2007
IEEE
223views Hardware» more  DATE 2007»
15 years 4 months ago
CARAT: a toolkit for design and performance analysis of component-based embedded systems
Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This pap...
Egor R. V. Bondarev, Michel R. V. Chaudron, Peter ...