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2007
IEEE
174views Hardware» more  DATE 2007»
15 years 4 months ago
ATLAS: a chip-multiprocessor with transactional memory support
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy T...
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 4 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
DATE
2007
IEEE
88views Hardware» more  DATE 2007»
15 years 4 months ago
Improve CAM power efficiency using decoupled match line scheme
Content addressable memory (CAM) is widely used in many applications that require fast table lookup. Due to the parallel comparison feature and high frequency of lookup, however, ...
Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
DATE
2007
IEEE
78views Hardware» more  DATE 2007»
15 years 4 months ago
Hardware scheduling support in SMP architectures
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
André C. Nácul, Francesco Regazzoni,...
DATE
2007
IEEE
160views Hardware» more  DATE 2007»
15 years 4 months ago
FPGA-based networking systems for high data-rate and reliable in-vehicle communications
The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automot...
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacop...