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2007
IEEE
92views Hardware» more  DATE 2007»
15 years 4 months ago
Test quality analysis and improvement for an embedded asynchronous FIFO
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
Tobias Dubois, Erik Jan Marinissen, Mohamed Aziman...
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
15 years 4 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
15 years 4 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 4 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 4 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...