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92
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DATE
2008
IEEE
91views Hardware» more  DATE 2008»
15 years 7 months ago
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation
Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems ning and v...
Nicola Bombieri, Nicola Deganello, Franco Fummi
61
Voted
DATE
2008
IEEE
85views Hardware» more  DATE 2008»
15 years 7 months ago
Improved Visibility in One-to-Many Trace Concretization
We present an improved algorithm for concretization of abstract eres in abstraction refinement-based invariant checking. The algorithm maps each transition of the abstract error ...
Kuntal Nanshi, Fabio Somenzi
80
Voted
DATE
2008
IEEE
91views Hardware» more  DATE 2008»
15 years 7 months ago
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams
We present several methods to generate modular code from synchronous hierarchical block diagrams. Modularity means code is generated for a given macro (i.e., composite) block inde...
Roberto Lublinerman, Stavros Tripakis
101
Voted
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
15 years 7 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
15 years 7 months ago
Sizing Rules for Bipolar Analog Circuit Design
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level o...
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann