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2008
IEEE
116views Hardware» more  DATE 2008»
15 years 7 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
15 years 7 months ago
Retargetable Code Optimization for Predicated Execution
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
Manuel Hohenauer, Felix Engel, Rainer Leupers, Ger...
66
Voted
DATE
2008
IEEE
66views Hardware» more  DATE 2008»
15 years 7 months ago
Optimal Margin Computation for At-Speed Test
— In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly highe...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
15 years 7 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
112
Voted
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
15 years 7 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne