—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...
Fast real-time feasibility tests and analysis algorithms are necessary for a high acceptance of the formal techniques by industrial software engineers. This paper presents a possi...
Victor Pollex, Steffen Kollmann, Karsten Albers, F...
—The compilation of imperative synchronous languages like Esterel has been widely studied, the separate compilation of synchronous modules has not, and remains a challenge. We pr...
This contribution shows and discusses the requirements and constraints that an industrial engineering process defines for the integration of hardware IP into the system developmen...
—The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space ...
Michael A. Kochte, Christian G. Zoellin, Michael E...