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2009
IEEE
144views Hardware» more  DATE 2009»
15 years 4 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
15 years 4 months ago
Improved worst-case response-time calculations by upper-bound conditions
Fast real-time feasibility tests and analysis algorithms are necessary for a high acceptance of the formal techniques by industrial software engineers. This paper presents a possi...
Victor Pollex, Steffen Kollmann, Karsten Albers, F...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
15 years 4 months ago
Separate compilation and execution of imperative synchronous modules
—The compilation of imperative synchronous languages like Esterel has been widely studied, the separate compilation of synchronous modules has not, and remains a challenge. We pr...
Eric Vecchié, Jean-Pierre Talpin, Klaus Sch...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
15 years 4 months ago
An automated flow for integrating hardware IP into the automotive systems engineering process
This contribution shows and discusses the requirements and constraints that an industrial engineering process defines for the integration of hardware IP into the system developmen...
Jan-Hendrik Oetjens, Ralph Görgen, Joachim Ge...
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
15 years 4 months ago
Test exploration and validation using transaction level models
—The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space ...
Michael A. Kochte, Christian G. Zoellin, Michael E...