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2009
IEEE
127views Hardware» more  DATE 2009»
15 years 4 months ago
Sequential logic synthesis using symbolic bi-decomposition
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Victor N. Kravets, Alan Mishchenko
DATE
2009
IEEE
141views Hardware» more  DATE 2009»
15 years 4 months ago
How to speed-up your NLFSR-based stream cipher
— Non-Linear Feedback Shift Registers (NLFSRs) have been proposed as an alternative to Linear Feedback Shift Registers (LFSRs) for generating pseudo-random sequences for stream c...
Elena Dubrova
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
15 years 4 months ago
Decoupling capacitor planning with analytical delay model on RLC power grid
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
Ye Tao, Sung Kyu Lim
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
15 years 4 months ago
Error correction in single-hop wireless sensor networks - A case study
—Energy efficient communication is a key issue in wireless sensor networks. Common belief is that a multi-hop configuration is the only viable energy efficient technique. In t...
Daniel Schmidt 0001, Matthias Berning, Norbert Weh...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 2 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...