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2009
IEEE
137views Hardware» more  DATE 2009»
15 years 4 months ago
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
Nicola Concer, Salvatore Iamundo, Luciano Bononi
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
15 years 4 months ago
Computation of IP3 using single-tone moments analysis
Intermodulation distortion is one of the key design requirements of Radio Frequency circuits. The standard approach for analyzing distortion using circuit simulators is to mimic m...
Dani Tannir, Roni Khazaka
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 4 months ago
Optimal sizing of configurable devices to reduce variability in integrated circuits
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) st...
Peter Wilson, Reuben Wilcock
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
15 years 4 months ago
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures
We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize the buffer require...
Jun Zhu, Ingo Sander, Axel Jantsch
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
15 years 4 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...