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2009
IEEE
85views Hardware» more  DATE 2009»
15 years 4 months ago
Faster SAT solving with better CNF generation
Boolean satisfiability (SAT) solving has become an enabling technology with wide-ranging applications in numerous disciplines. These applications tend to be most naturally encode...
Benjamin Chambers, Panagiotis Manolios, Daron Vroo...
87
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DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 4 months ago
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources
—As multiprocessor systems are increasingly used in real-time environments, scheduling and synchronization analysis of these platforms receive growing attention. However, most kn...
Mircea Negrean, Simon Schliecker, Rolf Ernst
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
15 years 4 months ago
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
: Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential ...
Sivaram Gopalakrishnan, Priyank Kalla
DATE
2009
IEEE
194views Hardware» more  DATE 2009»
15 years 4 months ago
A UML frontend for IP-XACT-based IP management
—IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these description...
Tim Schattkowsky, Tao Xie, Wolfgang Mueller
77
Voted
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
15 years 4 months ago
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian...