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DATE
2009
IEEE
16 years 4 days ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
136
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DATE
2009
IEEE
16 years 4 days ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
137
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DATE
2009
IEEE
15 years 9 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
173
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DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract--DNA self-assembly is emerging as the most promising technique for nanoscale self-assembly as it uses the simple, yet precise rules of DNA binding to create macroscale ass...
153
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DATE
2009
IEEE
16 years 4 days ago
2009
IEEE
— As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accou...