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2010
IEEE
124views Hardware» more  DATE 2010»
15 years 4 months ago
Reuse-aware modulo scheduling for stream processors
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
Li Wang, Jingling Xue, Xuejun Yang
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 4 months ago
AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs
Aggressive technology scaling has an ever-increasing adverse impact on the lifetime reliability of microprocessors. This paper proposes a novel simulation framework for evaluating...
Lin Huang, Qiang Xu
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
15 years 4 months ago
Enabling efficient post-silicon debug by clustering of hardware-assertions
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
Mohammad Hossein Neishaburi, Zeljko Zilic
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 4 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
15 years 4 months ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis